Aiwa CSD-MD50 Wartungshandbuch PDF herunterladen (Seite 41)

1 MNT0 O Monitor output pin.

2 MNT1 O Monitor output pin.

3 MNT2 O Monitor output pin.

4 MNT3 O Monitor output pin.

5 SWDT I Data input pin for micro-processor serial interface.

6 SCLK I Shift clock input pin for micro-processor serial interface.

7 XLAT I Latch input pin for micro-processor serial interface. Shut down: Latch.

8 SRDT O Data output pin for micro-processor serial interface.

9 SENS O Output internal status according to micro-processor serial interface address.

10 XRST I Reset input pin. "L": Reset.

11 SQSY O Disc sub-code Q synchronize / ADIP synchronize output.

12 DQSY O

When source of the digital in is set to CD or MD, output sub-code Q synchronize of

UbitCD or MD format.

13 RECP I Laser power switching input pin. "H": Record power. 'L": Playback power.

14 XINT O Intrusion demand output pin. "L" setting when intrusion demand status is generated.

15 TX I Record data output enable signal input pin. "H": Enable.

16 OSCI I Crystal oscillator circuit input pin.

17 OSCO O Crystal oscillator circuit output pin. (OSCI inverted output)

18 XTSL I

Switch input frequency of OSCI pin. (Connected to DVDD)

"H": 512Fs (22.5792MHz), "L": 1024Fs (45.158MHz).

19 NC – Not used. (Connected to DVDD)

20 DVSS – Digital GND.

21 DIN I Input digital audio interface signal.

22 DOUT O Output digital audio interface signal.

23 ADDT I Analog record input pin. (Connected to external A/D converter output)

24 DADT O REC monitor output pin / Output decode audio data.

25 LRCK O Output LRCK (44.1kHz) to external audio block.

26 XBCK O Output bit clock (2.8224MHz) to external audio block.

27 FS256 O Output 256Fs (11.2896MHz).

28 DVDD – Digital power supply.

29 A03 O Output address for external DRAM.

30 A02 O Output address for external DRAM.

31 A01 O Output address for external DRAM.

32 A00 O Output address for external DRAM.

33 A10 O Output address for external DRAM. (Not used)

34 A04 O Output address for external DRAM.

35 A05 O Output address for external DRAM.

36 A06 O Output address for external DRAM.

37 A07 O Output address for external DRAM.

38 A08 O Output address for external DRAM.

39 A11 O Output address for external DRAM. (Not used.)

Pin No. Pin Name I/O Description

IC, CXD2652AR

IC DESCRIPTION

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 73 74

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